A dual-port static random access memory (SRAM) cell requires at least eight transistors. In contrast, a traditional single-port SRAM cell requires only six transistors. As compared to a single-port SRAM cell, a dual-port SRAM cell requires two extra access transistors to accommodate the additional port. Because single-port SRAM is thus substantially denser than dual-port SRAM, “pseudo-dual-port” (PDP) SRAMs have been developed in which the single port of traditional SRAM is time-multiplexed to represent two separate ports.
Although pseudo-dual-port SRAM has higher density, this improved density comes at the cost of slower operation in that a single clock cycle must accommodate two access cycles to simulate the two ports of actual dual-port SRAM. The resulting multiplexing of the access port places timing demands on the sense amplifier. It is desirable to increase the operating speed of PDP SRAMs so that they can be used as an alternative to traditional dual-port SRAMs to increase density.
Accordingly, there is a need in the art for PDP SRAMs with increased operating speed.